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Agenda
2025 TECHNICAL PROGRAM Technical Program at-a-glance PROGRAM BOOKLET FULL CONFERENCE AT A GLANCE tuesday Plenary scheduleMonday, 17 March
5:00 – 7:00 pm
Conference Building Foyer
Sponsored by 
All registered attendees are encouraged to join us for the opening reception!
Workshops
Trusted Supplier Industry Day
Monday, March 17
8 am – 5 pm
The 15th Trusted Supplier Industry Day will be an interactive event with an opportunity for attendees to hear from key leaders and provide input on the critical issues facing our community. We have seen important changes since last year’s Industry Day. The CHIPS Program office accelerated funding for projects under the CHIPS and Science Act for the construction, expansion, or modernization of commercial facilities for the fabrication of leading-edge, current-generation, and mature-node semiconductors. DoD under the new administration will be examining and evaluating its approach to a microelectronics strategy and securing access to assured semiconductor supply chains. The Industry Day program will feature speakers who will address evolving microelectronics strategies, with a focus on innovation, security, and integrity. Speakers will also address work being done by the Trusted Supplier community to assess unification and collaboration in end-to-end trust, value propositions and approaches to trusted FPGA’s and third-party intellectual property. The Industry Day is being designed to provoke thoughtful conversations and up-to-date information on the many activities being pursued to restore U.S. leadership in semiconductor manufacturing with a semiconductor supply chain that considers security along with technical performance. Please join us on March 17th to add your voice to the discussion of the most critical electronics issues of the day.
On-Shore Advanced Packaging Capabilities Part Duex
Monday, March 17
8 am – 12 pm
The government teams will present technical overviews of currently funded on-shore advanced packaging efforts including Reshore Ecosystem for Secure Heterogeneous Advanced Packaged Electronics (RESHAPE), Defense Production Act Investment (DPAI), and DARPA Next Generation Microelectronics Manufacturing (NGMM) teams. Program overviews, interactive discussions, and presentations from vendors on their advanced packaging manufacturing capabilities will provide an opportunity for attendees to hear from key stakeholders and provide input on the critical issues facing the advanced packaging community. Awards have been made through the Industrial Base Analysis and Sustainment (IBAS) program, RESHAPE effort, to Osceola County Fl/Skywater/BRIDG and Micross Components. The DPAI program has awarded Calument and GreenSource Fabrication LLC. The T&AM State of the art Heterogeneous Integrated Packaging (SHIP) program awarded SHIP RF to Qorvo. Speakers will address key needs and developments in packaging to include Fan-Out Wafer Level Packaging (FOWLP), Wafer Prep and High-Density Interconnent/High Density Build-up (HDI/HDBU). Please join us on the afternoon of March 18th to hear the latest in government packaging capability investments and be part of the needs and challenges discussions for this advanced packaging community.
From Idea to Impact Workshop: Navigating the Startup Ecosystem
Monday, March 17
1:30 - 4:30 pm
Co-organized by Intel Capital, IQT, and GOMACTech
In a rapidly evolving technological landscape, startups are a key driving force behind innovation and in enabling the U.S. Department of Defense's (DOD) technical leadership. This half-day workshop is designed to empower emerging tech entrepreneurs by exploring how startups can commercialize cutting-edge technologies that not only disrupt markets but also enhance national security. Participants will gain insights into commercializing and scaling promising microelectronics technologies, the VC funding ecosystem, and gaining traction within the defense ecosystem. Through expert panels, interactive networking sessions, and a startup-led panel, the workshop will focus on creating opportunities for startups to connect and expand upon relationships within the systems providers and include a set of startups showcasing their innovations and impact on the defense sectors. This workshop offers a unique opportunity to connect with like-minded investors, innovators, industry leaders, and potential collaborators, to help drive forward the next generation of technology. The workshop will include talks introducing VC relative to GOMAC technology, partnering with VCs for Growth, a Q&A around advancing technologies for commercialization, a panel dedicated to discussing funding opportunities for commercialization, and startup presentations, following by a networking reception hosted by Intel Capital. Speakers and Panel Participants include and are not limited to Intel Capital, IQT, Booz Allen Hamilton, USC, and Lockheed Martin Ventures.
Panel Discussions
GOMACTech 2025 Panel Discussions
All panels take place in Room 107, Conference Building
Global Chip Traceability: Securing the Semiconductor Supply Chain for a Resilient Future
Wednesday, March 19
10:30 am
The Semiconductor Traceability and Market Provenance (STAMP) initiative aims to deliver traceability of every semiconductor and its capabilities through the supply chain to help deliver assured supply for critical infrastructure and economic security. This panel session will focus on the global chip traceability initiative, a critical development aimed at securing the semiconductor supply chain and enhancing its transparency, security, and resilience. Given the complexities of the global chip ecosystem and the growing geopolitical tensions, this session will explore the role of Global Chip IDs and their application in preventing counterfeiting, securing infrastructure, and ensuring export control compliance. Panelists will discuss the economic value created by chip traceability, the integration of lifecycle management tools, and the formation of cross-border public-private partnerships (PPPs) to support a scalable solution. The conversation will be grounded in how this aligns with the US and EU CHIPS Acts, and broader international cooperation efforts.
Microelectronics Transition Activities/Challenges within Program Offices
Wednesday, March 19
1:30 pm
Microelectronics transition is one of the greatest hurdles for any microelectronics development effort. This panel seeks to discuss topics related to the activities, challenges, and successes of microelectronics transition into program offices. Topics will include: use of tools for microelectronics digital engineering best practices, hardware and software co-development/testing/evaluation, and microelectronics integration into program roadmaps; to include, transition on-ramps, planning for upgradeability, obsolescence mitigation strategies that don’t include life-time buys, contracting, deliverables, technical data packages, and more. This panel will include government program office and industry perspectives. The goal of this panel is to fuel community discussions with program offices on how to enhance and accelerate transition of microelectronics.
Workforce Development and Mentorship
Wednesday, March 19
3:30 pm
The semiconductor industry is facing a significant shortage of skilled workers, prompting numerous workforce development initiatives. To make a sustainable impact, it's crucial to focus on other steps, including effective mentorship programs. Mentorship can be a critical component of workforce development, providing individuals with the tools and guidance needed to succeed and remain in the industry. However, challenges such as being intentional in mentorship efforts and matching mentors with mentees effectively must be addressed. This panel will explore the mentoring process, discussing both the positive aspects and the challenges. Panelists will highlight the top three successes and difficulties in this area.
Microelectronics Innovation - Strategies for Dual-Use Applications in US Government
Thursday, March 20
8:30 am
Given the diminishing pace of progress correlated with Moore's Law, a variety of new computing technologies have emerged, including analog processing, stochastic/probabilistic methods, neuromorphic architectures, quantum systems, and 3D integrated circuits. These technologies have the potential to provide significantly greater computational power while adhering to size, weight, and power (SWaP) constraints. However, they are frequently constrained to specific applications and face significant challenges requiring specialized architectures, software support, and integration with existing systems. To achieve meaningful impact with these innovative technologies, it is essential to engage in co-design across multiple domains, including materials, devices, architectures, algorithms, and systems. The complexity of these challenges means that many promising technologies struggle to gain widespread commercial viability and sustainability. Relying on a single application from the US Government (USG) is not enough to mature and sustain these emerging technologies. To address this issue, we need both technical and policy solutions that foster the development of technologies with a viable commercial market. This will ensure their sustainability while also meeting mission requirements. This panel will bring together experts from academia, national laboratories, commercial sectors, and government agencies to explore how the academic and USG communities can collaboratively advance emerging computing technologies for dual-use applications.
T&AM MPW Program
Thursday, March 20
10:30 am
The Trusted and Assured Microelectronics (T&AM) Program within OUSD Research & Engineering (R&E) aims to provide the U.S. warfighter with the State-of-the-Art (SOTA), assured microelectronics required to meet DoD system modernization goals. One of the primary objectives of the program is to enable access to commercial industry to develop and demonstrate SOTA designs that advance DoD initiatives. T&AM sponsors Multi-Project Wafer (MPW) run opportunities to enable access to SOTA US commercial foundries ≤ 14nm in support of the DoD microelectronics goals and to aid in developing DoD specific PDK’s and IP. Currently, T&AM sponsors MPW opportunities with Global Foundries and Intel Foundry Services. The program is available to relevant designs from the defense industrial base (DIB), gov’t labs, and academia.
The panel will provide an overview of T&AM MPW opportunities and a discussion of technologies currently sponsored.
USG Microelectronics Advanced Packaging Landscape
Thursday, March 20
1:30 pm
The performance demands of defense and commercial applications alike continue to drive innovation in microelectronics development, pushing Moore’s Law to the limit. At the same time, the need for high-performance, low-power compute across the electromagnetic spectrum calls for diverse solutions. Meeting the performance demands for these next generation systems requires significant innovation across the ecosystem. Complementary U.S. Government (USG) initiatives, such as DARPA’s Next-Generation Microelectronics Manufacturing (NGMM) program, are driving this innovation through advanced packaging, with a focus on national security. This panel will bring together leaders from active USG microelectronics programs working toward both near-term and over the horizon advances, to facilitate a conversation with the USG microelectronics community around their respective challenges and goals.
California DREAMS Hub/MOSIS 2.0
Thursday, March 20
3:30 pm
MOSIS 2.0 is the primary operational entity of CA DREAMS – the Southern California-based superhub of the Microelectronics Commons program. Fully launched in 2024, MOSIS 2.0 integrates the facilities of 3 DIB full-flow compound semiconductor fabs and 7 university nano-fabs. A multi-faceted engineering staff has been assembled that supports the full range of MPW-related and nano-fab process R&D projects within the hub, but also supports prototyping in other hubs’ facilities and commercial foundries. This panel has two purposes: First is to provide a brief introduction to MOSIS 2.0, its operation, range of services, and status to the microelectronics community represented by the audience. The second purpose is to provide the R&D community with the opportunity to discuss and provide input that will help MOSIS 2.0 refine, balance, and potentially expand its capabilities. To this end a panel of experts, representing different stake-holder elements of the micro-electronics R&D community will present their perspectives on the best way to optimize the accelerating impact of MOSIS 2.0.
GOMACTech 2025 Co-Located Events
Room 104
Intel18A Technology: The DIB Design Experience
Wednesday, 19 March, 10:30 am
The intent of the panel is to discuss Intel18A technology and the experience of four DIB companies in using the technology to design test chips as part of the RAMP-C Program. Intel provides an introductory overview of the technology as context for presentations by the DIB companies. Boeing and Northrop Grumman discuss their experience using the Intel18A design ecosystem to design multiple Intel18A test chips that include digital and mixed-signal circuit blocks. Trusted Semiconductor Solutions and Reliable Microsystems discuss their recent experience on-boarding with the design-stable Intel18A PDK and its associated design collateral. The panelists then field questions from the audience regarding the presentations and the Intel18A DIB design experience.
A Department of Defense (DoD) Microelectronics Roadmap
Wednesday, 19 March, 1:30 pm
A comprehensive DoD microelectronics roadmap would align investments among the services, increase supply chain resiliency, and ensure long-term strategic planning. Microelectronics are foundational to DoD weapon systems, communications platforms, intelligence capabilities, and more; a roadmap would help mitigate risks associated with foreign dependence and supply chains while promoting collaboration among the defense sector, industry, academia, and our allies. The DoD must anticipate and invest in emerging technologies to maintain the competitive edge over our adversaries; a roadmap would create milestones for innovation and drive government-wide adoption for security and performance standards in microelectronics. While DoD participates and contributes to industry and academic oriented roadmaps, there is increasingly a need for us to coordinate internally to maximize the efficacy of our research investments and the interoperability of our systems. Additionally, the roadmap would inform intellectual property protections, workforce development initiatives, and export controls. This DoD microelectronics roadmap is essential to maintain technological superiority, secure the supply chain, and guide investments effectively.
Commercial-Scale Modernization of Defense Microelectronics
Thursday, 20 March, 10:30 am
Defense microelectronics deployment to the warfighter has well-understood challenges in access to state-of-the-art. However, prototyping, acquisition, and technology refresh is siloed across DoD components, causing reuse inefficiency and supply chain limitations in a highly disaggregated defense market for low-volume/high-mix solutions. Aggregating tri-service capabilities would increase volume and offer lower-mix common platform approaches. Further, the overall cost of supply chain development infrastructure is reduced with enterprise solutions. Lastly, enhanced methodology best practices to improve reliability become viable with such an approach. This would lift the caliber of the defense microelectronics industry and workforce to rival that of commercial electronics. Speakers from government and industry will weigh in on novel approaches toward this goal.
Keynote Speakers
Microelectronics Commons: The New Battleground of Global Motorsport
This insightful overview contemplates the progression and development of microelectronics in auto racing, ranging from the more traditional platform of INDYCAR racing into the rapidly growing, fully sustainable, and all-electric FIA Formula E World Championship. Learn from a leader in the motorsports industry about how involving regulations and increased technology integration has led to software development being the new trackside weapon, both on and off the racetrack.
Roger Griffiths
Team Principal
Andretti Formula E, Andretti Extreme E
Having joined Andretti in the spring of 2014, Roger Griffiths serves as the team principal for Andretti Formula E and Andretti Extreme E. Griffiths’ vast background in many motorsports endeavors including Formula One, INDYCAR, American Le Mans Series, European Le Mans Series, and Super Touring Cars, Griffiths has led Andretti Formula E to 10 wins and 32 podiums across nine seasons. He also served as the technical director for Honda Performance Development, where he experienced success at the Indy 500 in 2012 and the 2013 Driver’s Championship. The UK native is an engineering graduate of Loughborough University of Technology (1991) and the year following his graduation, Griffiths earned his master’s degree in automotive product engineering at Cranfield Institute of Technology with a specialization in vehicle modeling and lap simulation.
More than Microchips
Whitney Mason
Director
Microsystems Technology Office (MTO)
Since the invention of the transistor in 1947 and the integrated circuit in 1958, microchips have fueled scientific advancements, manufacturing innovations, and economic growth for most of the modern era. Today, DARPA’s Microsystems Technology Office (MTO) will advance the next generation of microsystems to disrupt the underlying technology, disrupt current manufacturing, and create new markets. This disruption requires unique insight to discover fundamentally new ways of creating advanced circuits that will dramatically alter and exceed the current state-of-the-art in microsystems. This will involve using the power of light at the microscale in three dimensions with advanced photonics. It will involve harnessing quantum mechanical phenomena for sensors and computers that break traditional classical limits. It will involve developing a toolbox of organic and biological molecules and hybrid bioelectronics that will exploit living system phenomena and connect back to traditional microsystems. Finally, it will involve developing technologies to affordably, rapidly, and sustainably fabricate these and other microsystems to lead to a new domestic manufacturing ecosystem that will exploit commercial scaling and underpin strong domestic economic growth.
Whitney Mason is the director of the Microsystems Technology Office (MTO). Previously, she held the deputy director role in the agency’s Strategic Technology Office (STO) from June 2022 to October 2023. Prior to joining STO, Dr. Mason served as a program manager in MTO from November 2017 to May 2022. Her research interests include imaging sensors that provide multifunction capability. In particular, she is interested in novel device structures, optics, and electronics that enable new capabilities compared to current state-of-the-art imaging systems. Dr. Mason joined DARPA from the Army C5ISR Center, formerly the Army Communications-Electronics Research, Development and Engineering Center, where she was the director of the Science and Technology Division within the Night Vision and Electronic Sensors Directorate at Fort Belvoir, Virginia. In that role, she led a team of scientists and engineers in the pursuit of new and improved focal plane array materials and devices; advanced read-out circuits; and enhanced optical materials and designs, lasers, and image processing. Dr. Mason holds a doctor of philosophy degree in physics from the University of Oklahoma and a bachelor of science degree in physics from Georgetown University.
Jack S. Kilby Lecture Series
Advanced R&D for Mission Needs
Dr. Joshua Fryman
Intel Fellow, Head
Intel Government Technology R&D Group
Dr. Joshua Fryman is an Intel Fellow and heads Intel Government Technology’s R&D group, setting the strategy and priorities for all external R&D between Intel and Public Sector sponsor agencies or commercial entities. He joined IGT from the Office of the CTO under Greg Lavender.
Prior to his role in IGT, his work was primarily focused on applied R&D for commercial and government customers, focusing on problems that are 3-10 years out on the horizon. Throughout his career, Dr. Fryman has been engaged in multiple project types, from fabricating and testing circuits to designing microprocessor and system architectures, interconnects, packaging, compilers, runtimes, applications, and algorithms.
In his role as Chief Architect or Principal Investigator (PI), Dr. Fryman has led pre-exascale programs such as DARPA UHPC and DOE Fast Forward and Xstack. He has also played a pivotal role as PI for at-scale future AI and analytics programs such as DARPA HIVE, IARPA AGILE, and DOE’s Advanced Memory Technology efforts. His role as a PI also includes security programs such as DARPA GAPS and other appliances.
Dr. Fryman obtained his BS in Computer Engineering from the University of Florida and a PhD in Computer Architecture from Georgia Tech. Renowned for his insights in the field, he is a frequently invited speaker on microelectronics, systems, packaging, integration, and hardware-software co-design topics.
The NSTC: Leveraging Public-private Partnerships to Advance U.S.-led Semiconductor R&D, Workforce, and National Security
Program Management Office
Natcast
The National Semiconductor Technology Center (NSTC) is a public-private consortium established by the CHIPS and Science Act and is dedicated to semiconductor R&D in the United States. Operated by Natcast, the NSTC convenes industry, academia, and government from across the semiconductor ecosystem to address the most challenging barriers to continued technological progress in the domestic semiconductor industry, including the need for a skilled workforce. Natcast Program Management Office Director Salman Nasir shares insights into the once-in-a-lifetime opportunity presented by the NSTC, its activities to-date, and its impact on innovation, workforce, and economic and national security.
Mr. Salman Nasir is the director of the Program Management Office at Natcast, overseeing R&D programs. Previously, he was the Programs & Site Lead at Battelle's Dayton facility, managing Microelectronics Security Research and Hardware Assurance programs. He has over a decade of R&D experience particularly in microelectronic hardware, RF communication, EO/IR sensors, high-performance computing, and image processing. Mr. Nasir holds an MBA, an MS in Electrical Engineering, and a BS in Electrical Engineering. Mr. Nasir is a certified PMP® and Six Sigma Black Belt, with multiple industry and DoD awards, including the Defense Manufacturing Technology Achievement Award.
DoD Microelectronics – Transitioning Innovation in 2025 and Beyond
Dr. Carl E. McCants
Special Assistant to the Director
Darpa
In the March 2024 “National Strategy on Microelectronics Research” published by the Subcommittee on Microelectronics Leadership of the National Science and Technology Council,1one of the four goals and objectives is “Create a Vibrant Microelectronics Innovation Ecosystem to Accelerate the Transition of Research and Development to U.S. Industry”. This goal “is focused on the entire R&D landscape and presents strategies and actions to create a vibrant microelectronics innovation ecosystem to… support actions at each stage of the microelectronics technology development pathway… to build a virtuous cycle of microelectronics innovation.”2 The DoD faces unique challenges in developing, accessing, and utilizing microelectronics design, fabrication, packaging and assembly, characterization, and failure analysis capabilities needed to maintain and extend technological leadership in national security applications. This talk will explore the question “How should the DoD microelectronics ecosystem change to leverage and transition innovative capabilities that keep pace with or create the state of the art?”
[1] https://www.nitrd.gov/pubs/National-Strategy-on-Microelectronics-Research-March-2024.pdf
[2] https://www.nitrd.gov/pubs/National-Strategy-on-Microelectronics-Research-March-2024.pdf p.vi.
Dr. Carl E. McCants is a special assistant to the DARPA director, focusing on efforts to inform microelectronics policy and national strategies for microelectronics research and development.
Prior to his role at DARPA, he was the technical director of the Supply Chain and Cyber Directorate of the National Counterintelligence and Security Center (NCSC), in the Office of the Director of National Intelligence and a senior program manager at the Intelligence Advanced Research Projects Activity (IARPA).
From 2010 to 2012, he was a program manager in the Microsystems Technology Office at DARPA, focused on microelectronic integration and hardware assurance and reliability. From 2003 to 2009, he served as the chief technologist to the director of MTO, and special assistant to the DARPA deputy director.
From 1999 to 2003, McCants was a project manager at Agilent Technologies’ Semiconductor Products Group, and from 1988 to 1999, he was a development engineer at Hewlett-Packard’s Optical Communication Division.